A 59.5mW 4096x2160p Scalable/Multi-view Video Decoder Chip for Quad/3D Full HDTV and Video Streaming Applications



     A 59.5mW Scalable/Multi-view/H.264 multi-standard video decoder chip is implemented on a 3.88mm2 die with UMC 90nm CMOS. Through reconfigurable scheduling and optimized architecture, a low memory bandwidth and high throughput design is achieved. The proposed decoder has 3.38x higher throughput with 47% power reduction compared with the previous works.

Chip Spec




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