**** 2015 ********

[134] Yu-Jung Chen,Chao-Hsien Hsu , Chung-Yao Hung , Chia-Ming Chang , Shan-Yi Chuang , Shao-Yi Chien,and Liang-Gee Chen , "A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques", in IEEE Journal of Solid-State Circuits (JSSC) , vol.50, no.9, pp.2212-2223, September 2015.
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**** 2012 ********

[133] Chung-Te Li, Yen-Chieh Lai, Chien Wu, Sung-Fang Tsai, Tung-Chien Chen, Shao-Yi Chien, Liang-Gee Chen, "Brain-Inspired Framework for Fusion of Multiple Depth Cues", in Circuits and Systems for Video Technology, IEEE Transactions on, vol.PP, no.99, pp.1, October 2012.
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[132] Tung-Chien Chen, Wentai Liu and Liang-Gee Chen, "128-channel Neural Signal Processor with a Parallel-folding Structure in 90nm Process", in IEEE Journal of Signal Processing Systems.

[131] Yu-Chi Su, Keng-Yen Huang, Tse-Wei Chen, Yi-Min Tsai, Shao-Yi Chien and Liang-Gee Chen, "A 52mW Full HD 80-Degree Viewpoint Recognition SoC with Visual Vocabulary Processor for Wearable Vision Applications", in IEEE Journal of Solid State Circuit (JSSC), vol.47, no.4, pp.797-809, April 2012.
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[130] Tse-Wei Chen, Yu-Chi Su, Keng-Yen Huang, Yi-Ming Tsai, Shao-Yi Chien and Liang-Gee Chen, "Visaul Vocabulary Processor Based on Binary Tree Architecture for Full-HD Object Recognition", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, to be appear.

**** 2011 ********

[129] Hong-Hui Chen, Cheng-Yi Chiang, Tung-Chien Chen, Chien-Sheng Liu, Yu-Jie Huang, Shey-Shi Lu, Chii-Wann Lin and Liang-Gee Chen, "Analysis and Design of On-sensor ECG Processors for Realtime Detection of Cardiac Anomalies Including VF, VT, and PVC;, in Journal Of Signal Processing Systems, vol.65, no.2, pp.275-285, August 2011.
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[128] Shao-Yi Chien and Liang-Gee Chen, "Reconfigurable Morphological Image Processing Accelerator for Video Object Segmentation", in Journal of Signal Processing Systems.
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[127] Sung-Fang Tsai, Chao-Chung Cheng, Chung-Te Li, and Liang-Gee Chen, "A Real- Time 1080p 2D-to-3D Video Conversion System", in IEEE Transactions on Consumer Electronics, vol.57, no.2, pp.915-922, May 2011.
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**** 2010 ********

[126] Wei-Min Chao and Liang-Gee Chen, "Pyramid Architecture for 3840×2160 Quad Full High Definition 30 Frames/s Video Acquisition", in IEEE Transactions on Circuits and Systems for Video Technology , vol.20, no.11, pp.1499-1508, Nov. 2010.
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[125] Chao-Chung Cheng and Chung-Te Li and Liang-Gee Chen, "Video 2-D to 3-D conversion based on hybrid depth cueing", in Journal of the Society for Information Display , 2010.
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[124] Tse-Wei Chen and Chi-Sun Tang and Sung-Fang Tsai and Chen-Han Tsai and Shao-Yi Chien and Liang-Gee Chen, "Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis", in IEEE Journal of Solid State Circuit (JSSC), Vol. 45, No. 11, pp2321-2329, Nov. 2010.
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[123] Pei-Kuei Tsung and Li-Fu Ding and Wei-Yin Chen and Tzu-Der Chuang and Yu-Han Chen and Pai-Heng Hsiao and Shao-Yi Chien and Liang-Gee Chen, "Video Encoder Design for High Definition 3D Video Communication Systems", in IEEE Communication Magazine, 2010, vol. vol. 48, number Issue 4, pp. pp76-86.
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[122] Li-Fu Ding and W.-Y. Chen and P.-K. Tsung and T.-D. Chuang and P.-H. Hsiao and Y.-H. Chen and H.-K. Chiu and S.-Y. Chien and L.-G. Chen, "A 212MPixels/s 4096x2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications", in IEEE Journal of Solid State Circuits, 2010, pp. (invited paper).
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**** 2009 ********

[121] Chih-Chi Cheng and Chia-Hua Lin and Chung-Te Li and Liang-Gee Chen, "iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor", in IEEE Journal of Solid-State Circuits , 2009 , Invited paper, vol. 44, number 1, pp. 127-135 (Invited paper).
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[120] Chih-Chi Cheng and Po-Chih Tseng and Liang-Gee Chen, "Multi-Mode Embedded Compression Codec Engine for Power Aware Video Coding Systems", in IEEE Transactions Circuits and Systems for Video Technology , 2009, vol. 19, No.2, pp. 141-150.
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[119] Yu-Han Chen and Tung-Chien Chen and Chuan-Yung Tsai and Sung-Fang Tsai and Liang-Gee Chen, "Algorithm and Architecture Design of Power-oriented H.264/AVC Baseline Profile Encoder for Portable Devices", in IEEE Transactions on Circuits and Systems for Video Technology, 2009, vol. 19, No.8, pp. pp.1118-1128.
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**** 2008 ********

[118] Li-Fu Ding and Pei-Kuei Tsung and Shao-Yi Chien and Wei-Yin Chen and Liang-Gee Chen, "Content-Aware Prediction Algorithm with Inter-View Mode Decision for Multiview Video Coding", in IEEE Transactions on Multimedia , vol.10, no.8, pp.1553-1564.
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[117] Yi-Hau Chen and Chih-Chi Cheng and Tzu-Der Chuang and Ching-Yeh Chen and Shao-Yi Chien and Liang-Gee Chen, "Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine", in IEEE Transactions on Circuits and Systems for Video Technology, 2008, vol. 18, No.1, pp. 98-109.
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[116] Chia-Ho Pan and Ching-Yen Chien and Wei-Min Chao and Sheng-Chieh Huang and Liang-Gee Chen, "Architecture design of full HD JPEG XR encoder for digital photography applications", in IEEE Transactions on Consumer Electronics, 2008, vol. 54, number 3, pp. 963-971.
[Download]

[115] Yi-Hau Chen and Tung-Chien Chen and Shao-Yi Chien and Yu-Wen Huang and Liang-Gee Chen, "VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC ", in Journal of Signal Processing Systems, 2008, vol. 53, No. 3 , pp. 335-347.
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[114] Yi-Hau Chen and Shao-Yi Chien and Ching-Yeh Chen and Yu-Wen Huang and Liang-Gee Chen, "Analysis and Hardware Architecture Design of Global Motion Estimation ", in Journal of Signal Processing Systems, 2008, vol. 53, No. 3, pp. 285-300.
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[113] Yu-Han Chen and Tung-Chien Chen and Chuan-Yung Tsai and Sung-Fang Tsai and Liang-Gee Chen, "Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder", in The Journal of VLSI Signal Processing, 2008, vol. 50, No. 1.
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**** 2007 ********

[112] Chung-Jr Lian and Shao-Yi Chien and Chia-ping Lin and Po-Chih Tseng and Liang-Gee Chen, "Power-Aware Multimedia: Concepts and Design Perspectives", in IEEE Circuits and Systems Magazine, 2007, vol. 7, number 2, pp. 26-34.
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[111] Yu-Wei Chang and Chih-Chi Cheng and Chun-Chia Chen and Hung-Chi Fang and Liang-Gee Chen, "124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory", in IEEE Transactions on Circuits and Systems for Video Technology, 2007, vol. 17, number 4, pp. 398-406.
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[110] Tung-Chien Chen and Yu-Han Chen and Sung-Fang Tsai and Shao-Yi Chien and Liang-Gee Chen, "Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC", in IEEE Transactions on Circuits and Systems for Video Technology, 2007, vol. 17, number 5, pp. 568-577.
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[109] Tung-Chien Chen and Chuan-Yung Tsai and Yu-Wen Huang and Liang-Gee Chen, "Single Reference Frame Multiple Current Macroblocks Scheme for Multiple Reference Frame Motion Estimation in H.264/AVC", in IEEE Transactions on Circuits and Systems for Video Technology, 2007, vol. 17, number 2, pp. 242-247.
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[108] Chih-Chi Cheng and Chao-Tsung Huang and Ching-Yeh Chen and Chung-Jr Lian and Liang-Gee Chen, "On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform", in IEEE Transactions on Circuits and Systems for Video Technology, 2007, vol. 17, number 7, pp. 814-822.
[Download]

[107] Chia-Ho Pan and I. Hsien Lee and Sheng-Chieh Huang and Chung-Jr Lian and Liang-Gee Chen, "A Quality-of-Experience Video Adaptor for Serving Scalable Video Applications", in IEEE Transactions on Consumer Electronics, 2007, vol. 53, number 3, pp. 1130-1137.
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[106] Yu-Wei Chang and Hung-Chi Fang and Chun-Chia Chen and Chung-Jr Lian and Liang-Gee Chen, "Word-Level Parallel Architecture of JPEG 2000 Embedded Block Coding Decoder", in IEEE Transactions on Multimedia, 2007, vol. 9, number 6, pp. 1103-1112.
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**** 2006 ********

[105] Tung-Chien Chen and Hung-Chi Fang and Chung-Jr Lian and Chen-Han Tsai and Yu-Wen Huang and To-Wei Chen and Ching-Yen Chen and Yu-Han Chen and Chuan-Yung Tsai and Liang-Gee Chen, "Algorithm analysis and architecture design for HDTV applications - a look at the H.264/AVC video compressor system", in IEEE Circuits and Devices Magazine, 2006, vol. 22, number 3, pp. 22-31.
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[104] Ching-Yeh Chen and Chao-Tsung Huang and Yi-Hau Chen and Liang-Gee Chen, "Level C+ data reuse scheme for motion estimation with corresponding coding orders", in IEEE Transactions on Circuits and Systems for Video Technology, 2006, vol. 16, number 4, pp. 553-558.
[Download]

[103] Tung-Chien Chen and Shao-Yi Chien and Yu-Wen Huang and Chen-Han Tsai and Ching-Yeh Chen and To-Wei Chen and Liang-Gee Chen, "Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder", in IEEE Transactions on Circuits and Systems for Video Technology, 2006, vol. 16, number 6, pp. 673-688.
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[102] Li-Fu Ding and Shao-Yi Chien and Liang-Gee Chen, "Joint Prediction Algorithm and Architecture for Stereo Video Hybrid Coding Systems", in IEEE Transactions on Circuits and Systems for Video Technology, 2006, vol. 16, number 11, pp. 1324-1337.
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[101] Yu-Wen Huang and Bing-Yu Hsieh and Shao-Yi Chien and Shyh-Yih Ma and Liang-Gee Chen, "Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC", in IEEE Transactions on Circuits and Systems for Video Technology, 2006, vol. 16, number 4, pp. 507-522.
[Download]

[100] Ching-Yeh Chen and Shao-Yi Chien and Yu-Wen Huang and Tung-Chien Chen and Tu-Chih Wang and Liang-Gee Chen, "Analysis and architecture design of variable block-size motion estimation for H.264/AVC", in IEEE Transactions on Circuits and Systems I: Regular Papers, 2006, vol. 53, number 3, pp. 578-593.
[Download]

[99] Tung-Chien Chen and Yu-Wen Huang and Chuan-Yung Tsai and Bing-Yu Hsieh and Liang-Gee Chen, "Architecture Design of Context-Based Adaptive Variable-Length Coding for H.264/AVC", in IEEE Transactions on Circuits and Systems II: Express Briefs, 2006, vol. 53, number 9, pp. 832-836.
[Download]

[98] Yu-Wei Chang and Hung-Chi Fang and Chih-Chi Cheng and Chun-Chia Chen and Liang-Gee Chen, "Precompression Quality-Control Algorithm for JPEG 2000", in IEEE Transactions on Image Processing, 2006, vol. 15, number 11, pp. 3279-3293.
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[97] Ching-Yeh Chen and Yu-Wen Huang and Chia-Lin Lee and Liang-Gee Chen, "One-pass computation-aware motion estimation with adaptive search strategy", in IEEE Transactions on Multimedia, 2006, vol. 8, number 4, pp. 698-706.
[Download]

[96] Hung-Chi Fang and Yu-Wei Chang and Tu-Chih Wang and Chao-Tsung Huang and Liang-Gee Chen, "High-performance JPEG 2000 encoder with rate-distortion optimization", in IEEE Transactions on Multimedia, 2006, vol. 8, number 4, pp. 645-653.
[Download]

[95] Ching-Yeh Chen and Chao-Tsung Huang and Yi-Hau Chen and Shoa-Yi Chien and Liang-Gee Chen, "System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering", in IEEE Transactions on Signal Processing, 2006, vol. 54, number 10, pp. 4004-4014.
[Download]

[94] Hung-Chi Fang and Yu-Wei Chang and Chih-Chi Cheng and Liang-Gee Chen, "Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling", in IEEE Transactions on Signal Processing, 2006, vol. 54, number 12, pp. 4807-4816.
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[93] Yung-Chi Chang and Wei-Min Chao and Chih-Wei Hsu and Liang-Gee Chen, "Platform-Based MPEG-4 SOC Design for Video Communications", in The Journal of VLSI Signal Processing, 2006, vol. 42, number 1, pp. 7-19.
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[92] Yung-Chi Chang and Chih-Wei Hsu and Wei-Min Chao and Liang-Gee Chen, "Interactive Content-aware Video Streaming System with Fine Granularity Scalability", in The Journal of VLSI Signal Processing, 2006, vol. 44, number 1, pp. 117-134.
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[91] Shao-Yi Chien and Bing-Yu Hsieh and Yu-Wen Huang and Shyh-Yih Ma and Liang-Gee Chen, "Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems", in The Journal of VLSI Signal Processing, 2006, vol. 42, number 3, pp. 241-255.
[Download]

[90] Yu-Wen Huang and Ching-Yeh Chen and Chen-Han Tsai and Chun-Fu Shen and Liang-Gee Chen, "Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results", in The Journal of VLSI Signal Processing, 2006, vol. 42, number 3, pp. 297-320.
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**** 2005 ********

[89] P.-C Tseng and Y.-C. Chang and Y.-W. Huang and H.-C. Fang and C.-T. Huang and L.-G. Chen, "Advances in hardware architectures for image and video coding – a survey", in Proceedings of IEEE, 2005 , vol. 93, number no. 1, pp. 184-197.

[88] Shao-Yi Chien and Yu-Wen Huang and Ching-Yeh Chen and Hung-Hui Chen and Liang-Gee Chen, "Hardware architecture design of video compression for multimedia communication systems", in IEEE Communications Magazine, 2005, vol. 43, number 8, pp. 122-131.
[Download]

[87] Shih-Way Huang and Tsung-Han Tsai and Liang-Gee Chen, "Fast decomposition of filterbanks for the state-of-the-art audio coding", in IEEE Signal Processing Letters, 2005, vol. 12, number 10, pp. 693-696.
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[86] Yu-Lin Chang and Shyh-Feng Lin and Ching-Yeh Chen and Liang-Gee Chen, "Video de-interlacing by adaptive 4-field global/local motion compensated approach", in IEEE Transactions on Circuits and Systems for Video Technology, 2005, vol. 15, number 12, pp. 1569-1582.
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[85] Shao-Yi Chien and Shyh-Yih Ma and Liang-Gee Chen, "Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements", in IEEE Transactions on Circuits and Systems for Video Technology, 2005, vol. 15, number 9, pp. 1156-1169.
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[84] Hung-Chi Fang and Yu-Wei Chang and Tu-Chih Wang and Chung-Jr Lian and Liang-Gee Chen, "Parallel embedded block coding architecture for JPEG 2000", in IEEE Transactions on Circuits and Systems for Video Technology, 2005, vol. 15, number 9, pp. 1086-1097.
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[83] Chao-Tsung Huang and Po-Chih Tseng and Liang-Gee Chen, "Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method", in IEEE Transactions on Circuits and Systems for Video Technology, 2005, vol. 15, number 7, pp. 910-920.
[Download]

[82] Yu-Wen Huang and Bing-Yu Hsieh and Tung-Chien Chen and Liang-Gee Chen, "Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder", in IEEE Transactions on Circuits and Systems for Video Technology, 2005, vol. 15, number 3, pp. 378-401.
[Download]

[81] Chao-Tsung Huang and Po-Chih Tseng and Liang-Gee Chen, "Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform", in IEEE Transactions on Signal Processing, 2005, vol. 53, number 4, pp. 1575-1586.
[Download]

[80] P.-J. Lee and Homer H. Chen and W.-J. Wang and L.-G. Chen, "Feature-Based Error Concealment for Object-Based Video", in IEICE Transactions Visual Communications, 2005, vol. E88-B, number no. 6, pp. 2616-2626.

[79] Yung-Chi Chang and Chao-Chih Huang and Wei-Min Chao and Liang-Gee Chen, "An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System", in The Journal of VLSI Signal Processing, 2005, vol. 41, number 2, pp. 183-191.
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[78] Chao-Tsung Huang and Po-Chih Tseng and Liang-Gee Chen, "VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters", in The Journal of VLSI Signal Processing, 2005, vol. 40, number 2, pp. 175-188.
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[77] Chao-Tsung Huang and Po-Chih Tseng and Liang-Gee Chen, "VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization", in The Journal of VLSI Signal Processing, 2005, vol. 40, number 3, pp. 343-353.
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[76] Po-Chih Tseng and Chao-Tsung Huang and Liang-Gee Chen, "Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems", in The Journal of VLSI Signal Processing, 2005, vol. 41, number 1, pp. 35-47.
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**** 2004 ********

[75] Yu-Wen Huang and Shao-Yi Chien and Bing-Yu Hsieh and Liang-Gee Chen, "Global elimination algorithm and architecture design for fast block matching motion estimation", in IEEE Transactions on Circuits and Systems for Video Technology, 2004, vol. 14, number 6, pp. 898-907.
[Download]

[74] Shyh-Feng Lin and Sheng-Chieh Huang and Feng-Sung Yang and Chung-Wei Ku and Liang-Gee Chen, "Power-efficient FIR filter architecture design for wireless embedded system", in IEEE Transactions on Circuits and Systems II: Express Briefs, 2004, vol. 51, number 1, pp. 21-25.
[Download]

[73] Shih-Way Huang and Tsung-Han Tsai and Liang-Gee Chen, "A low complexity design of psycho-acoustic model for MPEG-2/4 advanced audio coding", in IEEE Transactions on Consumer Electronics, 2004, vol. 50, number 4, pp. 1209-1217.
[Download]

[72] Shao-Yi Chien and Yu-Wen Huang and Bing-Yu Hsieh and Shyh-Yih Ma and Liang-Gee Chen, "Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques", in IEEE Transactions on Multimedia, 2004, vol. 6, number 5, pp. 732-748.
[Download]

[71] Chao-Tsung Huang and Po-Chih Tseng and Liang-Gee Chen, "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform", in IEEE Transactions on Signal Processing, 2004, vol. 52, number 4, pp. 1080-1089.
[Download]

**** 2003 ********

[70] Shao-Yi Chien and Yu-Wen Huang and Liang-Gee Chen, "Predictive watershed: a fast watershed algorithm for video segmentation", in IEEE Transactions on Circuits and Systems for Video Technology, 2003, vol. 13, number 5, pp. 453-461.
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[69] Yu-Wen Huang and Shyh-Yih Ma and Chun-Fu Shen and Liang-Gee Chen, "Predictive line search: an efficient motion estimation algorithm for MPEG-4 encoding systems on multimedia processors", in IEEE Transactions on Circuits and Systems for Video Technology, 2003, vol. 13, number 1, pp. 111-117.
[Download]

[68] Chung-Jr Lian and Kuan-Fu Chen and Hong-Hui Chen and Liang-Gee Chen, "Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000", in IEEE Transactions on Circuits and Systems for Video Technology, 2003, vol. 13, number 3, pp. 219-230.
[Download]

[67] Pei-jun Lee and Liang-Gee Chen, "Error concealment algorithm using interested direction for JPEG 2000 image transmission", in IEEE Transactions on Consumer Electronics, 2003, vol. 49, number 4, pp. 1395-1401.
[Download]

[66] Shyh-Feng Lin and Yu-Ling Chang and Liang-Gee Chen, "Motion adaptive interpolation with horizontal motion detection for deinterlacing", in IEEE Transactions on Consumer Electronics, 2003, vol. 49, number 4, pp. 1256-1265.
[Download]

[65] C.-J. Lian and Z.-L. Yang and H.-C. Chang and L.-G. Chen, "Hardware-efficient architecture design for zerotree coding in MPEG-4 still texture coder", in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, 2003, (SCI & EI) (S35-91C-09a, S35-91C-11a, S35-90C-34a, TSMC 0.35), vol. E86-A, no. 2, , pp. 472–479.

**** 2002 ********

[64] Hao-Chieh Chang and Yung-Chi Chang and Yi-Chu Wang and Wei-Ming Chao and Liang-Gee Chen, "VLSI architecture design of MPEG-4 shape coding", in IEEE Transactions on Circuits and Systems for Video Technology, 2002, vol. 12, number 9, pp. 741-751.
[Download]

[63] Shao-Yi Chien and Shyh-Yih Ma and Liang-Gee Chen, "Efficient moving object segmentation algorithm using background registration technique", in IEEE Transactions on Circuits and Systems for Video Technology, 2002, vol. 12, number 7, pp. 577-586.
[Download]

[62] Tu-Chih Wang and Hung-Chi Fang and Liang-Gee Chen, "Low-delay and error-robust wireless video transmission for video communications", in IEEE Transactions on Circuits and Systems for Video Technology, 2002, vol. 12, number 12, pp. 1049-1058.
[Download]

**** 2001 ********

[61] Jun-Fu Shen and Tu-Chih Wang and Liang-Gee Chen, "A novel low-power full-search block-matching motion-estimation design for H.263+", in IEEE Transactions on Circuits and Systems for Video Technology, 2001, vol. 11, number 7, pp. 890-897.
[Download]

[60] Po-Cheng Wu and Liang-Gee Chen, "An efficient architecture for two-dimensional discrete wavelet transform", in IEEE Transactions on Circuits and Systems for Video Technology, 2001, vol. 11, number 4, pp. 536-545.
[Download]

[59] Chi-Kuang Chen and Po-Chih Tseng and Yung-Chil Chang and Liang-Gee Chen, "A digital signal processor with programmable correlator array architecture for third generation wireless communication system", in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001, vol. 48, number 12, pp. 1110-1120.
[Download]

[58] Po-Chih Tseng and Chi-Kuang Chen and Liang-Gee Chen, "CDSP: an application-specific digital signal processor for third generation wireless communications", in IEEE Transactions on Consumer Electronics, 2001, vol. 47, number 3, pp. 672-677.
[Download]

[57] Chien-Yu Chen and Zhong-Lan Yang and Tu-Chih Wang and Liang-Gee Chen, "A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform", in The Journal of VLSI Signal Processing, 2001, vol. 28, number 3, pp. 151-163.
[Download]

[56] Tsung-Han Tsai and Ren-Jr Wu and Liang-Gee Chen, "A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core", in The Journal of VLSI Signal Processing, 2001, vol. 29, number 3, pp. 255-265.
[Download]

**** 2000 ********

[55] Tsung-Han Tsai and Liang-Gee Chen, "A novel architecture of inverse quantization and multichannel processing for MPEG-2 audio decoding", in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000, vol. 47, number 1, pp. 75-78.
[Download]

[54] Ruei-Xi Chen and Liang-Gee Chen and Lilin Chen, "System design consideration for digital wheelchair controller", in IEEE Transactions on Industrial Electronics, 2000, vol. 47, number 4, pp. 898-907.
[Download]

[53] Hao-Chieh Chang and Jiun-Ying Jiu and Li-Lin Chen and Liang-Gee Chen, "A Low Power 8 x 8 Direct 2-D DCT Chip Design", in The Journal of VLSI Signal Processing, 2000, vol. 26, number 3, pp. 319-332.
[Download]

**** 1999 ********

[52] Shyh-Yih Ma and Liang-Gee Chen, "A single-chip CMOS APS camera with direct frame difference output", in IEEE Journal of Solid-State Circuits, 1999, vol. 34, number 10, pp. 1415-1418.
[Download]

[51] Sheng-Chieh Huang and Liang-Gee Chen, "A LOG-EXP still image compression chip design", in IEEE Transactions on Consumer Electronics, 1999, vol. 45, number 3, pp. 812-819.
[Download]

**** 1998 ********

[50] Yeong-Kang Lai and Liang-Gee Chen, "A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm", in IEEE Transactions on Circuits and Systems for Video Technology, 1998, vol. 8, number 2, pp. 124-127.
[Download]

[49] Yeong-Kang Lai and Yeong-Lin Lai and Yuan-Chen Liu and Po-Cheng Wu and Liang-Gee Chen, "VLSI implementation of the motion estimator with two-dimensional data-reuse", in IEEE Transactions on Consumer Electronics, 1998, vol. 44, number 3, pp. 623-629.
[Download]

[48] Yuan-Chen Liu and Yeong-Kang Lai and Tsung-Han Tsai and Po-Cheng Wu and Liang-Gee Chen, "VLSI implementation of visual block pattern truncation coding", in IEEE Transactions on Consumer Electronics, 1998, vol. 44, number 3, pp. 490-499.
[Download]

[47] Po-Cheng Wu and Liang-Gee Chen and Yeong-Kang Lai, "A block shifting method for reduction of blocking effects in subband/wavelet image coding", in IEEE Transactions on Consumer Electronics, 1998, vol. 44, number 1, pp. 170-177.
[Download]

**** 1997 ********

[46] Mei-Juan Chen and Liang-Gee Chen and Ro-Min Weng, "Error concealment of lost motion vectors with overlapped motion compensation", in IEEE Transactions on Circuits and Systems for Video Technology, 1997, vol. 7, number 3, pp. 560-563.
[Download]

[45] Yung-Pin Lee and Thou-Ho Chen and Liang-Gee Chen and Mei-Juan Chen and Chung-Wei Ku, "A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method".

[44] Ruei-Xi Chen and Liang-Gee Chen and Mei-Juan Chen and Tsung-Han Tsai, "An I-phone system design and implementation with a portable speech coding coprocessor", in IEEE Transactions on Consumer Electronics, 1997, vol. 43, number 4, pp. 1262-1269.
[Download]

[43] Tsung-Han Tsai and Liang-Gee Chen and Yuan-Chen Liu, "A novel MPEG-2 audio decoder with efficient data arrangement and memory configuration", in IEEE Transactions on Consumer Electronics, 1997, vol. 43, number 3, pp. 598-604.
[Download]

[42] Chun-Te Chen and Liang-Gee Chen and Jue-Hsuan Hsiao, "A bit-level pipelined VLSI architecture for the running order algorithm", in IEEE Transactions on Signal Processing, 1997, vol. 45, number 8, pp. 2140-2144.
[Download]

[41] Yee-Wen Chen and Liang-Gee Chen and Mei-Juan Chen, "Jointly Optimal Region-Classified Adaptive Vector Quantization for Very Low Bit Rate Video Coding", in The Journal of VLSI Signal Processing, 1997, vol. 17, number 2, pp. 189-200.

**** 1996 ********

[40] M.-J. Chen and L.-G. Chen and K.-N. Cheng and M.-C. Chen, "Efficient hybrid tree/linear array architectures for block-matching motion estimation algorithms", in IEE Proceedings - Vision, Image and Signal Processing, 1996, vol. 143, number 4, pp. 217-222.
[Download]

[39] Po-Cheng Wu and Liang-Gee Chen and Tzi-Dar Chiueh, "Scalable implementation scheme for multirate FIR filters and its application in efficient design of subband filter banks", in IEEE Transactions on Circuits and Systems for Video Technology, 1996, vol. 6, number 4, pp. 407-410.
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[38] Ming-Hwa Chan and Wen-Ta Lee and Mao-Chao Lin and Liang-Gee Chen, "IC design of an adaptive Viterbi decoder", in IEEE Transactions on Consumer Electronics, 1996, vol. 42, number 1, pp. 52-62.
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[37] C.-T. Chen and L.-G. Chen, "A novel architecture for Lempel-Ziv-based data compression", in IEEE Transactions on Consumer Electronics, 1996, (SCI & EI).

[36] Chun-Te Chen and Liang-Gee Chen and Jue-Hsuan Hsiao, "VLSI implementation of a selective median filter", in IEEE Transactions on Consumer Electronics, 1996, vol. 42, number 1, pp. 33-42.
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[35] Hsu-Tung Chen and Po-Cheng Wu and Yeong-Kang Lai and Liang-Gee Chen, "A multimedia video conference system: using region base hybrid coding", in IEEE Transactions on Consumer Electronics, 1996, vol. 42, number 3, pp. 781-786.
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[34] Chung-Wei Ku and Liang-Gee Chen and Chang-Hong Chen and Juing-Yin Jiu and Chau-Tan Huang, "Investigation of a visual telephone prototyping on personal computers", in IEEE Transactions on Consumer Electronics, 1996, vol. 42, number 3, pp. 750-759.
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[33] Yeong-Kang Lai and Liang-Gee Chen and Hsu-Tung Chen and Mei-Juan Chen and Yung-Pin Lee and Po-Cheng Wu, "A novel video signal processor with programmable data arrangement and efficient memory configuration", in IEEE Transactions on Consumer Electronics, 1996, vol. 42, number 3, pp. 526-534.
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[32] Sheng-Chieh Huang and Liang-Gee Chen and Thou-Ho Chen, "A 32-bit logarithmic number system processor", in The Journal of VLSI Signal Processing, 1996, vol. 14, number 3, pp. 311-319.
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**** 1995 ********

[31] T.-H. Chen and Y.-P. Lee and L.-G. Chen, "Concurrent error detection in array multipliers by BIDO", in IEE Proceedings - Computers and Digital Techniques, 1995, vol. 142, number 6, pp. 425-430.
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[30] Mei-Juan Chen and Liang-Gee Chen and Tzi-Dar Chiueh and Yung-Pin Lee, "A new block-matching criterion for motion estimation and its implementation", in IEEE Transactions on Circuits and Systems for Video Technology, 1995, vol. 5, number 3, pp. 231-236.
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[29] Jue-Hsuan Hsiao and Liang-Gee Ghen and Tzi-Dar Chiueh and Chun-Te Chen, "High throughput CORDIC-based systolic array design for the discrete cosine transform", in IEEE Transactions on Circuits and Systems for Video Technology, 1995, vol. 5, number 3, pp. 218-225.
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[28] Wen-Ta Lee and Ming-Hwa Chan and Liang-Gee Chen and Mao-Chao Lin, "A single-chip Viterbi decoder for a binary convolutional code using an adaptive algorithm", in IEEE Transactions on Consumer Electronics, 1995, vol. 41, number 1, pp. 150-159.
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[27] Tsung-Han Tsai and Thou-Ho Chen and Liang-Gee Chen, "An MPEG audio decoder chip", in IEEE Transactions on Consumer Electronics, 1995, vol. 41, number 1, pp. 89-96.
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[26] Liang-Gee Chen and Yeu-Shen Jehng and Tzi-Dar Chiueh, "Pipeline interleaving design for FIR, IIR, and FFT array processors", in The Journal of VLSI Signal Processing, 1995, vol. 10, number 3, pp. 275-293.
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**** 1994 ********

[25] Tzi-Dar Chiueh and Tser-Tzi Tang and Liang-Gee Chen, "Vector quantization using tree-structured self-organizing feature maps", in IEEE Journal on Selected Areas in Communications, 1994, vol. 12, number 9, pp. 1594-1599.
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[24] Liang-Gee Chen and Yuan-Chen Liu, "A high quality MC-OBTC Codec for video signal processing", in IEEE Transactions on Circuits and Systems for Video Technology, 1994, vol. 4, number 1, pp. 92-98.
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[23] M.-J. Chen and L.-G. Chen and T.-D. Chiueh, "One-dimensional full search motion estimation algorithm for video coding", in IEEE Transactions on Circuits and Systems for Video Technology, 1994, vol. 4, number 5, pp. 504-509.
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[22] Her-Ming Jong and Liang Gee Chen and Tzi-Dar Chiueh, "Parallel architectures for 3-step hierarchical search block-matching algorithm", in IEEE Transactions on Circuits and Systems for Video Technology, 1994, vol. 4, number 4, pp. 407-416.
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[21] Her-Ming Jong and Liang-Gee Chen and Tzi-Dar Chiueh, "Accuracy improvement and cost reduction of 3-step search block matching algorithm for video coding", in IEEE Transactions on Circuits and Systems for Video Technology, 1994, vol. 4, number 1, pp. 88-90.
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[20] Lih-Gwo Jeng and Liang-Gee Chen, "Rate-optimal DSP synthesis by pipeline and minimum unfolding", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994, vol. 2, number 1, pp. 81-88.
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**** 1993 ********

[19] C.-W. Ku and L.-G. Chen and T.-D. Chiueh, "Cache vector quantisation algorithm in video compression", in Electronics Letters, 1993, vol. 29, number 16, pp. 1423-1424.
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[18] L.-G. Jeng and D.-Y. Bai and L.-G. Chen, "Graphical block-diagram based programming environment for a DSP silicon compiler", in IEE Proceedings - Circuits, Devices and Systems, 1993, vol. 140, number 5, pp. 313-318.
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[17] Thou-Ho Chen and Liang-Gee Chen, "Concurrent error-detectable butterfly chip for real-time FFT processing through time redundancy", in IEEE Journal of Solid-State Circuits, 1993, vol. 28, number 5, pp. 537-547.
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[16] Liang-Gee Chen and Yuan-Chen Liu and Tzi-Dar Chiuch and Yung-Pin Lee, "A real-time video signal processing chip", in IEEE Transactions on Consumer Electronics, 1993, vol. 39, number 2, pp. 82-92.
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[15] Yeu-Shen Jehng and Liang-Gee Chen and Tzi-Dar Chiueh, "An efficient and simple VLSI tree architecture for motion estimation algorithms", in IEEE Transactions on Signal Processing, 1993, vol. 41, number 2, pp. 889-900.
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**** 1992 ********

[14] H.-M. Jong and L.-G. Chen and T.-D. Chiueh, "ROM-based special purpose multiplication and its applications", in Electronics Letters, 1992, vol. 28, number 8, pp. 718-720.
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[13] H.-M. Jong and L.-G. Chen and T.-D. Chiueh, "DCT-based interframe coding for video codec", in Electronics Letters, 1992, vol. 28, number 4, pp. 411-413.
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[12] Y.-S. Jehng and L.-G. Chen and T.-D. Chiueh, "A motion estimator for low bit-rate video codec", in IEEE Transactions on Consumer Electronics, 1992, vol. 38, number 2, pp. 60-69.
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[11] Thou-Ho Chen and Liang-Gee Chen and Yeu-Shen Jehng, "Design and analysis of VLSI-based arithmetic arrays with error correction", in International Journal of Electronics, 1992, vol. 72, number 2, pp. 253-271.
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[10] Lih-Gwo Jeng and Liang-Gee Chen, "Rate-optimal static scheduling for recursive DSP algorithms by retiming and unfolding", in International Journal of Electronics, 1992, vol. 73, number 4, pp. 687-701.
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**** 1991 ********

[9] L.-G. Chen and T.-H. Chen, "Fault-tolerant serial-parallel multiplier", in IEE Proceedings - Computers and Digital Techniques, 1991, vol. 138, number 4, pp. 276-280.
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[8] Liang-Gee Chen and Wai-Ting Chen and Yeu-Shen Jehng and Tzi-Dar Chiuch, "An efficient parallel motion estimation algorithm for digital image processing", in IEEE Transactions on Circuits and Systems for Video Technology, 1991, vol. 1, number 4, pp. 378-385.
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[7] Yeu-Shen Jehng and Liang-Gee Chen and Tai-Ming Parng, "ASG: Automatic schematic generator", in Integration, the VLSI Journal, 1991, vol. 11, number 1, pp. 11-27.
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**** 1987 ********

[6] L.-G. Chen and J.-Y. Lee and J.-F. Wang, " Hierarchical functional verification for cell-based design styles", in IEE Proceedings G. Electronic Circuits and Systems, 1987, vol. 134, pp. 103-110.
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[5] L.-G. Chen and R.-J. Huang and J.-F. Wang and J.-Y. Lee, "An interactive net connectivity check strategy", in IEEE Transactions on Circuits and Systems for Video Technology, 1987, vol. 34, number 9, pp. 1135-1137.
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**** 1986 ********

[4] L.-G. Chen and J.-Y. Lee and J.-F. Wang and K.-T. Chen, "Fast execution for circuit consistency verification", in Integration, the VLSI Journal, 1986, vol. 4, number 3, pp. 239-262.
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**** 1985 ********

[3] Thou-Ho Chen and Yung-Pin Lee and Liang-Gee Chen, "VLSI-based array dividers with concurrent error detection", in International Journal of Electronics, 1985, vol. 78, number 6, pp. 1139-1148.
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**** 1983 ********

[2 ] L.-G. Chen and C.-Y. Chang and Y.-K. Su and T.-S. Wu, "Numerical analysis of an injection laser with stripe geometry", in Optics and Lasers in Engineering, 1983, vol. 4, pp. 195-202.
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**** 1981 ********

[1 ] C.-Y. Chang and Y.-K. Su and M.-K. Lee and L.-G. Chen and M.-P. Houng, "Characterization of GaAs epitaxial layers by low pressure MOVPE using TEG as Ga source", in Journal of Crystal Growth, 1981, vol. 55, number 1, pp. 24-29.
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