Lab Honor

Chip Gallery - 2009

40: A 212MPixels/s 40962160p Multiview Video Encoder Chip for 3D/Quad HDTV Applications
Designer	Pei-Kuei Tsung
Technology	TSMC 90nm 1P9M CMOS
Operating Voltage	Core 1.2V, I/O 3.3V
Temperature	25℃
Chip Size	3.95mm x 2.90mm
Gate Count	1732K equivalent NAND2 gates
On-chip SRAM	H.264/AVC Multiview Extension/High Profile @Level5.1
View Scalibility	4096x2160p for 1 view
	1920x1080p for up to 3-views
	1280x720p for up to 7 views
Maximum Throughput	212Mpixels/sec, 830k MB/sec@280MHz
ME/DE search Range H/V	[-256,+255]/[-256,+255]
Operating Frequency & Power Consumption	522mW@280MHz for 4096x2160p/24fps/Single view
	366mW@166MHz for 1920x1080p/30fps/Stereo views
	317mW@144MHz for 1280x720p/30fps/Quad views
	148mW@81MHz for 1920x1080p/30fps/Single view
	58mW@36MHz for 1280x720p/30fps/Single view
	ISSCC

39: CACHE-BASED INTEGER MOTION/DISPARITY ESTIMATION FOR QUAD-HD H.264/AVC AND HD MULTIVIEW VIDEO CODING
Designer	Pei-Kuei Tsung
Technology	TSMC 90nm CMOS LOGIC Low Power LowK Cu 1P9M 1.2&2.5V
Chip Size	2.1mm x 2.1mm
Working Frequency	300MHz
Power	265mW@300MHz, 1.2V
Operating Voltage	1.2V
Gate Count	230K equivalent NAND2 gates
SRAM	8KBytes
Processing Capability	4096x2160 single view H.264 1080p stereo MVC 720p four-view MCV
	ICASSP